1. Field of the Invention
The present invention relates to a method and apparatus adapted to apply a high test voltage to a semiconductor device, and more particularly, to a method and apparatus for controlling a high voltage generator for use in a wafer burn-in test.
2. Discussion of Related Art
A burn-in test is typically applied to a volatile semiconductor memory device such as a dynamic random access memory and the like (DRAM). The burn-in test accelerates failure modes if they exist, by applying short duration high voltage and temperature stresses to the device under test. After the test application, the device is evaluated. Chips containing weak or faulty cells or chips having electronic characteristics deviating from acceptable distributions are screened out.
A wafer burn-in test is disclosed in a patent to Yamamoto (U.S. Pat. No. 6,372,528) issued Apr. 16, 2002. The burn-in test requires a stress voltage VPP that is higher than the voltages VDD used by the device during normal operation. The stress voltage VPP is generally generated by a high voltage generator that is provided on the semiconductor memory device itself.
FIG. 1 is a block diagram of a high voltage generator. Referring to FIG. 1, the high voltage generator 100 comprises a ring oscillator 10, a charge pump 20, and a level detecting circuit 30. The level detecting circuit 30 generates a detection signal by comparing a high voltage VPP with a reference voltage Ref. The detection signal represents an extent of a level rise or a level drop of the high voltage VPP. The ring oscillator 10 generates clocks CK,/CK for use in generating the high voltage VPP responsive, in turn, to the detection signal outputted from the level detecting circuit 30. The charge pump 20 performs a charge pumping operation responsive to the clocks CK,/CK and thus outputs the high voltage VPP that traces to the reference voltage Ref.
The high voltage generator 100 is widely used in wafer burn-in test, and threshold voltage loss compensation caused by driving a DRAM wordline or by using an N-type MOS transistor.
To reduce wafer burn-in test time, a high level of an external voltage source EVDD is applied to the semiconductor memory device. The external voltage source EVDD rises at a same slope as a high voltage. When the external power voltage EVDD is output at too high a level, a gate oxide film of a memory cell transistor breaks down or has a punch through phenomenon.
That is, in the high voltage generator of FIG. 1, when a voltage difference between the external power voltage EVDD and the reference voltage VRef is more than a predetermined voltage difference during burn-in, the reference voltage is increased proportionately to an increase of the external power voltage EVDD, which causes an increase in the high voltage applied for the burn-in test. These increases breakdown the gate oxide film of the transistor or cause a punch through phenomenon.
A semiconductor memory device employs a substrate bias voltage generator for generating a substrate bias voltage. The substrate bias voltage (hereinafter “VBB”) has a negative voltage level as compared to the voltage source VDD. The VBB generator, therefore, is also termed a negative drop voltage generator.
Three primary reasons for supplying the bias voltage VBB to the substrate exist. First, the bias voltage VBB prevents circuit elements P/N junctions from partially forward biasing, thereby preventing data loss, latch up, and the like in memory cells. Second, the bias voltage VBB stabilizes the device by reducing threshold voltage changes related to a back gate effect in a MOS transistor. Finally, the bias voltage VBB improves operating speed by increasing a threshold voltage of a parasitic MOS transistor. The increased threshold voltage improves the consistency of a channel stop implant provided under a field oxide layer.
The negative drop voltage generator comprises a ring oscillator, a charge pump, and a level detector, similarly to the construction of the high voltage generator.
The level detector detects the negative drop voltage VBB received by feedback, and outputs a detection signal that represents the extent of a level rise or fall of the negative drop voltage VBB. The ring oscillator generates clock signals corresponding to the detection signal outputted from the level detector. The charge pump performs a charge pumping operation responsive to the clock signals, to thus output, as the VBB, the negative drop voltage VBB having a negative voltage level.
During wafer burn-in, the bias voltage VBB is applied substantially higher or lower than at any other time including during operation. If a voltage lower than the bias voltage VBB is applied externally through a VBB pad, the level detector within the negative drop voltage generator can continuously operate on the basis of a difference between the external and internally generated voltage level. The result is an irregular VBB on some regions of the substrate. That is, VBB appears inconsistently on the substrate. This, in turn, results in reduced test coverage for a refresh operation and a consequent reduction in device reliability.
Accordingly, a need remains for a high voltage generator that maintains constant a voltage during predetermined modes of operations such as burn-in. And a need remains for an improved negative drop voltage generator.